With the PAM4 encoding technology, the amount of information transmitted on 50G PAM4-based optical transceivers within each sampling cycle doubles. A 25G optical component can be used to achieve a 50Gbps transmission rate, reducing the costs of optical transceivers.
50G PAM4 applies to multiple scenarios, such as single-lane 50GE PAM4 optical transceivers, 4-lane 200GE optical transceivers, and 8-lane 400GE optical transceivers.
This section introduces the functions of a single-lane 50GE PAM4 optical transceiver.
Working principle of a 50GE PAM4 optical transceiver
The working principle of a 50GE PAM4 optical transceiver is described as follows:
In the transmit direction, the PAM4 encoding chip aggregates two 25Gbit/s NRZ signals into one 25GBaud PAM4 signal. The laser drive chip amplifies the PAM4 signal, and the 25Gbps laser converts the electrical signal into a 25GBaud(50Gbps) single-wavelength optical signal.
In the receive direction, the detector converts the 25GBaud single-wavelength optical signal into an electric signal. The electric signal is shaped and amplified, and then output to the PAM4 decoding chip. The PAM4 decoding chip converts the signal into two 25Gbps NRZ signals.
The 50GE PAM4 optical transceiver uses the QSFP28 encapsulation mode, LC optical interfaces, and single-mode optical fibers. The transmission distance is 10km or 40km, and the maximum power consumption is 4.5W.
The performance of transmitters and receivers on optical interfaces of 50GE PAM4 optical transceivers must comply with the IEEE 802.3bs and IEEE 802.3cd standards.
An optical transceiver provides N 25Gbps electrical interfaces. For a 50GE optical transceiver, the two electrical lanes transmit TX1/RX1 and TX2/RX2 signals specified in the SFF-8436_MSA standards. The performance of electrical interfaces must comply with the CEI-28G-VSR LAUI-2 standard.
The optical transceiver with a transmission rate of 50Gbps on a single wavelength supports 50GE, 200GE, and 400GE interfaces. The following table lists the parameters for the 50GE, 200GE, and 400GE technical solutions.
50G PAM4 optical transceivers use mature 25Gbps optoelectronic chips to deliver cost-effective solutions. In 50GBASE-LR 10 km scenarios, uncooled Direct Modulated Laser (DML) Transmitter Optical Sub-Assemblies (TOSAs) with TO packaging are used. Such a solution features mature technologies, low costs, low power consumption, and easy mass production. The linear DML driver chip can convert input PAM4 voltage electric signals into current signals that can directly drive lasers. Such chips deliver a high bandwidth and output large drive current. Their maximum working rate can reach 28GBaud. At the receive end, Receiver Optical Sub-Assemblies (ROSAs) with TO packaging are used. 25Gbps pins and linear Trans-Impedance Amplifier (TIA) chips are integrated to the ROSAs.
Optical components in 50GBASE-LR scenarios
In 50GBASE-ER 40 km scenarios, 25Gbps Electro-absorption Modulated Laser (EML) TOSAs with BOX packaging are used. External cavity modulated Distribution Feed-Back (DFB) lasers, isolators, monitoring diodes, thermistors, and EML components are integrated to the TOSAs and driven by voltage signals. Such a solution features wide linear domains, high ER, high output optical power, and low TDECQ. Linear EML drive chips can amplify input PAM4 signals and output them to next EMLs. These chips provide a high bandwidth, a small jitter, an adjustable output gain, and a working rate up to 28GBaud. At the receive end, APD ROSAs with TO packaging are used. 25Gbps APDs and linear TIA chips are integrated into the ROSAs. Such ROSAs feature high sensitivity and apply to 40km long-distance transmission.
Optical components in 50GBASE-ER scenarios
PAM4 codec chips perform conversion between NRZ signals and PAM4 signals inside transceivers. In the transmit direction, PAM4 chips shape, amplify, and convert two 25Gbps NRZ signals output by boards into one 25GBaud PAM4 signal. In the receive direction, PAM4 chips use the Analog to Digital Converter (ADC) and Digital Signal Processing (DSP) technology to decode the one 25GBaud signal to two 25Gbps NRZ signals.
The optical components and chips of PAM4 transceivers are very different from those of NRZ transceivers. The following table lists the differences between 50G QSFP28 LR and 25G SFP28 LR.
The main difference lies in laser drive chips, TIA chips, and data processing chips.
Since PAM4 code has four types of level logic, the laser drive chips and TIA chips are capable of linear outputs. NRZ transceivers output signals in amplitude limiting mode.
PAM4 transceivers use DSP to implement conversion between a 50G PAM4 signal and two 25Gbps NRZ signals. NRZ transceivers transmit data using Clock & Data Recovery (CDR) chips only.
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