September 7, 2026, Shenzhen, China. – As the optical interconnect industry enters a critical transition period from 800G to 1.6T, the industry has been seeking an optimal solution between ultra-low-power LPO/LRO and high-margin full-DSP architectures. With its differentiated advantages of flexibility, controllability, balanced power consumption, and robust link performance, the half-DSP heterogeneous Hybrid architecture is moving beyond vendor innovation and onto the system evaluation lists of global hyperscalers.
Microsoft and Meta, which have long played leading roles in defining next-generation data center interconnect standards, have already completed system simulations and feasibility assessments through international open technology forums such as OIF and OCP. Their core concept is to deploy retimed channels and linear-receive channels on the same port, using high-quality retimed channels with DSP-based compensation as a link reference, while assisting the switch SerDes in performing coordinated equalization optimization for the linear channels. This approach aims to control overall system power consumption while improving the interference resistance and transmission robustness of parallel optical links.
Unlike the single-design logic of fully symmetric LRO or LPO implementations, the Hybrid-channel system concept breaks the conventional either-or technology choice.
- Purely linear solutions offer power advantages, but are highly sensitive to link margin and strongly dependent on cabling quality and switch-chip capabilities;
- Full-DSP solutions provide strong link stability, but come with higher overall system power consumption;
- Hybrid retimed architecture introduces a new compromise: some channels retain independent signal compensation and link diagnostic capabilities, while the remaining channels use linear reception to achieve power savings, enabling a dynamic balance among performance, power consumption, and operational maintainability.
The following illustrates the complete clock-recovery principle of Hybrid LRO (4 full-DSP channels + 4 linear-receive channels):
Hybrid Architecture Diagram
- Four channels with RX DSP: Clock recovery is completed inside the optical module
- Four LRO linear channels: The module has no CDR; all clock recovery is performed by the switch SerDes, with two operating modes (Independent Mode / Coordinated Reference Mode)
Interpretation 1: CDR Principle of the Four RX-DSP Channels (Module-Side Closed-Loop Recovery)
Process: Optical signal → PD optical-to-electrical conversion → TIA amplification → ADC sampling → CDR circuit inside the module RX DSP
- The ADC samples the received analog signal using a locally free-running high-speed clock.
- The CDR continuously compares the edge phase of the sampled data with the ideal data phase and calculates the phase error.
- Through digital loop filtering, the sampling-clock phase is dynamically adjusted to align with the signal transition edges.
- An aligned, low-jitter recovered clock and clean data stream are then output.
- At the same time, error statistics and jitter margin are monitored, with diagnostic information reported through CMIS.
Interpretation 2: Basic Principle of the Four Linear LRO Channels (Standard Independent Mode)
These four channels have no ADC, on-chip DSP, or CDR.
Process: Optical signal → PD → Linear TIA → High-speed analog electrical signal directly output to the switch ASIC
- Each SerDes lane inside the switch has its own independent CDR.
- Each lane independently captures the analog-signal edges and completes clock-phase locking.
- By default, the clocks of all eight channels operate independently without referencing one another.
Key Interpretation: Enhanced Coordinated Mode (System-Level Optimization Unique to the Hybrid Architecture)
With support from switch-level algorithms:
- The four module-side DSP channels first establish a stable set of high-quality reference clock and phase information.
- The ASIC uses this validated clock reference as the initial phase prediction and jitter constraint for the CDRs of the four linear channels.
- The CDRs of the linear channels no longer need to blindly search for the correct phase from scratch. Instead, the phase-search range is narrowed, enabling faster clock recovery while reducing clock offset and jitter variation among parallel channels.
While hyperscalers have so far focused primarily on system-level architecture analysis and simulation validation, GIGALIGHT has moved ahead of the industry by turning this innovative concept into an engineered, practical solution.
GIGALIGHT Hybrid Product Portfolio：
- 1.6T OSFP-HRO 2×DR4 Silicon Photonics Transceiver
- 800G OSFP-HRO 2×DR4 Silicon Photonics Transceiver
- 800G OSFP HYBRID VR8-AOC Active Optical Cable
- 800G OSFP HYBRID PSM8-AOC Active Optical Cable
Based on this Hybrid-channel concept, GIGALIGHT’s Hybrid half-DSP heterogeneous silicon photonics transceivers adopt a differentiated channel architecture: four channels retain full RX-DSP compensation capability, while the other four channels employ a linear-receive architecture with DSP pre-emphasis on the transmit side.
The product portfolio covers two major form factors: 800G/1.6T OSFP-HRO 2×DR4 and HYBRID PSM8-AOC. These products transform forward-looking concepts discussed in open industry forums into testable, scalable, and mass-producible commercial hardware solutions.
From the perspective of comprehensive networking value in complex real-world data-center environments, while Microsoft and Meta are driving the implementation of LRO standards, major industry players are also beginning to evaluate the system-level value of a Hybrid retimed architecture with greater practical deployment potential.
This Hybrid retimed solution points directly to the Hybrid half-DSP technology roadmap.
In One Sentence
The key difference between a Hybrid linear channel and a conventional LRO channel is that pure LRO lacks system-level clock and phase synchronization capabilities. This is precisely the underlying value of Hybrid technology, giving it strong potential to become a mainstream technology direction for next-generation private AI computing networks.
About GIGALIGHT
As an open optical networking explorer, GIGALIGHT integrates the design, manufacturing, and sales of both active and passive optical devices and subsystems. The company’s product portfolio includes III-V optical modules, silicon photonics modules and silicon-based NPO/CPO engines, liquid-cooled optical modules, passive optical components, Active Optical Cables (AOCs), Direct Attach Cables (DACs), coherent optical communication modules, OPEN DCI BOX subsystems based on coherent and O-band DWDM optical modules, and UHD SDI video optical transceivers. GIGALIGHT focuses on applications including AI data centers, 5G transport networks, metropolitan WDM transmission, and ultra-HD broadcast and video, positioning itself as an innovative designer of high-speed optical interconnect hardware solutions.