15Nov, 2023

Emerging Packaging Technologies: A Technical Deep Dive

Advanced packaging stands out as a major highlight in the ‘More than Moore’ era. As chip miniaturization becomes increasingly challenging and costly at each process node, engineers are opting to place multiple chips into advanced packaging rather than struggle to further shrink the chips.

3D packaging

In 2.5D packaging, bare die stacks or side-by-side placements rest atop an interposer with silicon vias (TSVs). The base, or the interposer, provides connectivity between chips. In 3D IC packaging, logic die stacks together or with memory die stacks without constructing a large System on Chip (SoC). Connections between bare dies occur through an active interposer, while in 2.5D IC packaging, components are stacked on the interposer using conductive bumps or TSVs. On the other hand, 3D IC packaging connects multiple layers of silicon wafers using TSV-enabled components.

Chiplet packaging

A series of modular chips in a chip library can be integrated into packaging using die-to-die interconnect technology. Chiplets represent another form of 3D IC packaging, enabling the heterogeneous integration of CMOS and non-CMOS components. In essence, they are smaller System on Chips (SoCs) or chiplets rather than large SoCs in the package. Breaking down large SoCs into smaller chips boasts higher yields and lower costs compared to a single bare die. Chiplets empower designers to leverage various IPs without concern for process nodes or manufacturing technologies. They can use diverse materials, including silicon, glass, and laminates, in chip fabrication.

Fan-out (FO) packaging

In FO packaging, connections fan out across the chip surface, providing more external I/O. It embeds bare dies entirely in epoxy molding compound (EMC), eliminating process flows like wafer bumps, underfill, flip chips, cleaning, underfill spraying, and curing, thus bypassing the need for an interposer, simplifying heterogeneous integration. Compared to other packaging types, FO technology offers smaller packages with more I/O. In 2016, it enabled Apple to integrate TSMC’s packaging technology, housing its 16nm application processor and mobile DRAM into one package for the iPhone 7, becoming a technological standout.

Fan-out wafer-level packaging (FOWLP)

This technology is an enhancement of wafer-level packaging (WLP), offering more external connections for silicon chips. It embeds chips into EMC, constructs a high-density redistribution layer (RDL) on the wafer surface, and applies solder balls, forming a reconstituted wafer. Typically, treated wafers are first cut into individual bare dies, then dispersed on a carrier structure, and the gaps are filled to form a reconstituted wafer. FOWLP provides numerous connections between the package and the application circuit board, and due to the larger substrate than bare dies, the spacing between the dies is, in fact, more lenient.

1Nov, 2023

Emerging Trends in 400G and 800G: Low-Power Solutions for High-Speed Networks

As Serdes technology drives data centers into the era of 400G and 800G, port power consumption has become a hot topic in the industry. Low-power 400G/800G interconnection solutions have been successively introduced, attracting wide attention in the industry and being widely regarded as a key technology for AI and machine learning in smart data centers.

1. CPO Aims to Address Next-Generation Bandwidth and Power Challenges

With the continuous acceleration of bandwidth in network and computing structures, innovation is required in system and chip architecture to mitigate the slowdown of Moore’s Law. Meanwhile, copper interconnects are rapidly reaching their bandwidth distance limits. Silicon photonics is crucial for sustaining rapid data growth and high-bandwidth applications. Co-Packaged Optics (CPO) involves co-packaging switch chip ASICs and optoelectronic engines (optical transceivers) on the same substrate, with the optical engines placed as close to the ASIC as possible to minimize high-speed electrical channel losses and impedance discontinuities. This enables the use of faster, lower-power off-chip I/O drivers. Using CPO not only achieves networking but also facilitates GPU-to-GPU interconnects, resource pooling, and memory disaggregation. It meets the requirements of AI/ML training clusters with high bandwidth and radix connections, the lowest per-bit cost, and the highest power efficiency.

2. Linear Direct-Drive Pluggable Modules Also Reduce Power Consumption

In the era of 400G and 800G, in addition to pluggable optical modules and CPO solutions, Linear Direct Drive (also known as linear drive) pluggable 400G/800G optical modules became a research hotspot at OFC in March of this year. The biggest advantage of this optical module solution is that it eliminates the need for DSP chips, significantly reducing the power consumption and latency of signal processing at the module level.

GPU servers serving applications such as AI and machine learning provide excellent computing power but also result in increased server power consumption. The high-speed interconnection of 400G/800G leads to a corresponding increase in the power consumption of optical modules and network equipment. Both CPO and linear direct-drive pluggable modules may be interconnection solutions for future smart data centers, providing the lowest system-level power by eliminating all possible active components from the interconnect.

24Oct, 2023

Decoding the Potential – 400G Optical Modules for Next-Gen DCI

From the data center network architecture perspective, transitioning from existing 100G solutions to meet the same-scale data center’s non-blocking network throughput has posed several challenges. Achieving this objective requires adding more ports, expanding rack space to accommodate servers and switches, and providing more server rack space. This approach is not only uneconomical but also significantly increases the complexity of the network architecture.

In contrast, transitioning from 100G to 400G is a more cost-effective way to provide higher bandwidth for data centers while reducing network architecture complexity. Furthermore, following the natural progression of network equipment development, when the interface speed increases fourfold to reach 400G, given mature device and transceiver technologies, the cost of a 400G network device typically amounts to only about 50% of the cost of four 100G devices and interfaces.

400G Optical Modules in Data Center

400G has already become ubiquitous in data center applications.

400G already become a must-have optical communication solution in DCI scenarios.

400G becomes the first choice for Hyperscale in POD interconnects.

Note: POD (Point of Delivery) is a distribution point that is used to facilitate resource pooling in a data center. To achieve this, a physical data center is typically divided into one or more physical zones, with each zone referred to as a POD. Thus, POD is a physical concept and represents the fundamental deployment unit of a data center. Typically, one piece of physical equipment can only belong to one POD.

ToR-Server, 100G Downlink 400G Uplink

Market Forecast and Iteration Direction of 400G in Data Center Technology

Market Forecast for 400G and Higher Speed Optical Modules

According to Light Counting’s projections for 400G and 800G-related products, SR/FR series optical modules are expected to be the primary growth products in data centers and internet centers:

The forecast indicates that 400G rate optical modules will be deployed on a large scale in 2023 and will account for the majority of optical module (40G and above rate) sales in 2025:

Data includes all ICP and Enterprise Data Centers

400G Optical Module Iteration Trends

With the physical layer single-lane electrical port speed reaching 112Gbps, data center networks will face significant challenges in network system design, equipment design, key component design, and more.

In this context, on June 13, 2021, the QSFP112 MSA (Multi-Source Agreement) group officially released the new QSFP112 specification 1.0. A total of 31 companies came together to support the QSFP112 MSA, with founding members including companies like Accelink Technologies, Alibaba, Amphenol, Baidu, Credo, H3C, Hisense, and others, to meet the industry’s demand for high-speed, high-density network solutions. The MSA will significantly help traditional QSFP users upgrade their link bandwidth to 400G per port with lower costs and shorter transition times.

From the different perspectives of 112G high-speed system design, the study of high-speed system design, system test methodology, high-speed interconnect system simulation, printed circuit board design for next-generation devices, high-speed backplane connectors, I/O connectors, and high-speed copper cables design and application for network devices under 112G SerDes are described in several aspects. All these efforts are aimed at accelerating the technological innovation of 112G SerDes-based networking devices.

In China, major domestic internet companies like Alibaba, Baidu, JD.com, ByteDance, and Kuaishou, while still primarily using 25G or 56G electrical ports in their current data center architectures, are jointly planning for high-speed electrical interfaces based on the 112G SerDes for their next-generation data centers.

In the optical module industry, GIGALIGHT has introduced 400G QSFP112 AOC/VR4/SR4 modules. Similarly, other companies such as Accelink, InnoLight, and Eoptolink have introduced their own 400G QSFP112 products and initiated validation plans with internet companies.

400G QSFP112 SR4/FR4/DR4 modules operating at 112Gbps SerDes speeds will undoubtedly be massively deployed during the process of upgrading from 100G to 400G in next-generation data centers.

31Aug, 2023

What a Linear Drive Module is?

Amidst the high-speed optical module landscape, the incorporation of DSP chips for signal processing has been the norm. These chips, featuring ADC/DAC, FEC, retiming, reshaping, adaptive equalization, and more, hold immense power, yet their potency comes at the cost of significant power consumption and expenses. A typical 7nm DSP in a 400G optical module consumes around 4W, constituting 50% of the module’s power consumption.

DSP Function Block Diagram

The following figure shows the power consumption breakdown of a 400G ZR optical module, with a similar scenario for an IMDD.

As a response to the need for efficiency, the revolutionary concept of Linear-drive technology emerged.

How can the power consumption and cost impact caused by DSP be mitigated?

By forgoing DSP within the optical module and integrating its functions into switching chips, a streamlined design emerges. The result? A compact configuration housing only driver and TIA components. Diverging from the traditional driver and TIA functions, those in the Linear Photonic Optics (LPO) architecture include CTLE and Equalization features, facilitating signal compensation. Notably, the Linear Drive concept obviates the need for retiming, eliminating non-linear processes and thus dubbed the Non-retimed module.

LPO’s merits encompass several facets:

Low Power Consumption: LPO yields a 50% reduction in power consumption compared to pluggable optical modules, aligning closely with CPO power levels.

The overall power consumption of the switch system will be reduced by about 25 percent, as below.

Low Latency: Omitting DSP significantly reduces system latency, ideal for latency-sensitive scenarios like inter-GPU communication within High-Performance Computing (HPC) centers.
Cost Efficiency: The absence of 5nm/7nm DSP chips translates to cost savings. In an 800G module, the Bill of Materials (BOM) cost totals around $600-$700, with DSP chips accounting for approximately $50-$70. While EQ integration within Driver and TIA adds $3-$5, the total system cost reduction amounts to around 8%.
Hot-Pluggability: LPO retains the convenience and reliability of pluggable modules, leveraging established optical module supply chains. This distinguishes LPO from CPO, which is still less widely adopted due to reliability and cost considerations.

Comparison of various dimensions of conventional optical modules, LPOs and CPOs

In summary, LPO represents a novel approach with its unique advantages and ongoing challenges.

Integration of DSP Chips: To implement LPO, there’s a need to integrate DSP chips into switches, which requires the involvement of switch chip manufacturers. The LPO concept has also stirred the competition among DSP chip manufacturers, such as Broadcom and Inphi.
New Protocols and Testing Methods: Introducing LPO necessitates the development of new protocols and testing methods. The Optical Internetworking Forum (OIF) is currently working on defining the CEI-112G-LINEAR standard to address this need.
Applicability and Distance: One concern is whether LPO is suitable for longer distances, potentially reaching kilometers. As DSP chips are no longer present in the module, there may be a decrease in error performance, leading to a reduction in transmission distance.

While several companies showcased their linear-drive solutions, particularly during OFC 2023, and launched LPO options post-event, the transition from technical discussions to widespread adoption is ongoing. The introduction of LPO underscores the industry’s pursuit of low-power, low-cost, high-speed optical modules.