PAM4 - GIGALIGHT

24Jul, 2025

Gigalight 1600G CPO Engine — Powering the Future of AI Connectivity

What has been done?
This design offers excellent scalability: the future 1600G CPO can be expanded from the existing 16-channel architecture to 32 channels, supporting 3200G CPO. The per-channel data rate can be flexibly configured as 100G PAM4 or 200G PAM4, significantly enhancing overall bandwidth capacity.
The Gigalight 1600G CPO adopts an advanced, highly integrated 2.5D hybrid packaging architecture combining Wire Bond (WB) and Flip Chip technologies. This significantly reduces the package size and overall footprint, improves system performance, lowers power consumption, increases integration density, and enables higher transmission speeds.

Electrical Interface Standard: OlF CE1-112G-XSR
Optical Interface Standard: lEEE-802.3bs 400GBASE-DR4
Software standard: OlF-CMlS-05.3

What’s the significant commercial contribution?

1600G CPO refers to next-generation integrated optical link technology capable of delivering
approximately 1.6Tbps (1600Gbps) per port. By co-packaging the optical engine with the switching ASIC, this design significantly improves bandwidth density and shortens the electrical signal path compared to traditional pluggable optics.
Based on recent industry data, its commercial value, market trends, technological positioning, and challenges can be summarized as follows:

1.Significant energy savings and reduced power consumption
2.Improved bandwidth density
3.Meets the demands of next-generation AI/HPC high-performance clusters

What’s the outlook?

CPO is regarded as the next-generation interconnect technology. Leading companies are actively deploying co-packaged optics (CPO), with the market expected to reach \$5 billion by 2030. Industry giants such as NVIDIA have already entered the CPO field.
Julie Sheridan, the company’s CTO, cited LightCounting data showing that the data center optical interconnect market will grow from about \$10 billion in 2024 to \$30 billion by 2030.

What is the competitive positioning?

1.Versus Pluggable Modules:
Current pluggable optical modules (such as OSFP and QSFP-DD800) support speeds up to 1.6–3.2Tbps, with mature ecosystems and ease of maintenance. For example:

1600G OSFP228 DR8 has power consumption <30W (3nm DSP expected <25W)
1600G OSFP-XD DR8 <25W
Our 1600G CPO DR16 consumes less than 16W, making it significantly more power- and size-efficient than traditional optical modules.

2.LPO (Linear Pluggable Optics) as a Transitional Solution:
LPO modules omit DSP chips, cutting power consumption by 30–50%. Some industry leaders (e.g., Arista CTO) see LPO as a power-efficient compromise that doesn’t require changes to existing architecture. Current 800G OSFP DR8 LPO modules consume less than 9W.
However, LPO cannot match CPO in bandwidth density or energy efficiency and is likely just a mid-term stopgap.

3.Key Players:
The main CPO players currently include leading chipmakers like Broadcom, NVIDIA, and Marvell. Traditional network vendors (e.g., Cisco, Arista, Juniper) are currently leaning toward LPO or high-performance pluggables. Industry analysts note that trends over the next 2–3 years will determine which technology path becomes dominant.

Please include a description of challenges that might create headwinds.

1.High Structural Complexity and Packaging Precision:
CPO requires extremely precise packaging. For instance, fibers must be precisely aligned with the silicon photonics engine, and heat density increases significantly. Even if total power drops in a 51.2Tbps CPO switch, heat per unit area rises, necessitating advanced cooling like cold plate liquid cooling.

2.Maintenance and Reliability Issues:
CPOs are not hot-swappable. If the optical engine fails, the entire system must be returned for repair, resulting in a much higher mean time to repair (MTTR) than pluggable optics. While traditional modules may have a failure rate of 100 per million hours, a CPO module failure incurs significantly higher replacement costs and maintenance challenges.

3.Lack of Standardization and Supply Chain Risk:
CPO is currently developed with proprietary standards by a few vendors, and the industry has not yet adopted a universally compatible interface. This increases the risk of vendor lock-in during deployment.

4.Cost and Market Uncertainty:
CPO is still more expensive than traditional solutions. Although it offers lower power consumption, the initial deployment cost is high. In the event of an economic slowdown or delayed adoption, the CPO supply chain may face idle capacity or financial losses.

5.Threat from Alternative Technologies:
Some experts argue that despite its advanced capabilities, CPO’s structural complexity leaves room for emerging interconnect technologies to eventually surpass it. Additionally, continued optimization of traditional pluggable solutions (e.g., LPO/ LRO) may narrow the performance gap.

Product Overview

Introduction to Gigalight’s 1600G CPO Silicon Photonic Engine Based on Linear Direct-Drive Technology:

The linear silicon photonic 1600G CPO engine adopts a SOCKET slot packaging format and integrates LPO (Linear Pluggable Optics) direct-drive technology. By eliminating the DSP, the linear CPO silicon photonic engine significantly reduces both system-level power consumption and cost.

On the transmitter (TX) side, the optical output ranges from 0 to 3 dBm, with an extinction ratio between 4 and 5 dB. The TDECQ is less than 2.5 dB, typically falling between 1 and 2 dB.The operating wavelength range is from 1304.5 nm to 1317.5 nm, with an SMSR of ≥30 dB. The receiver (RX) side has an OMA sensitivity of less than -5.5 dBm.

Electrical Interface Standard: OlF CE1-112G-XSR
Optical Interface Standard: lEEE-802.3bs 400GBASE-DR4
Software standard: OlF-CMlS-05.3

Key Specifications

The 1600G CPO linear silicon photonic engine features the following optical parameters:

Transmitter (TX) optical output: 0 to 3 dBm
Extinction ratio: 4 to 5 dB
TDECQ: <2.5 dB, typically between 1 and 2 dB
Wavelength range: 1304.5 nm to 1317.5 nm
SMSR: ≥30 dB
Receiver (RX) OMA sensitivity: < -5.5 dBm

The eye diagram is shown below:

Internal Structure of the Product

Adopts advanced hybrid packaging technology.

This design offers excellent scalability. The current 16-channel architecture of the 1600G CPO can be expanded to 32 channels in the future, enabling support for 3200G CPO. Each channel can be flexibly configured for either 100G PAM4 or 200G PAM4, significantly enhancing overall bandwidth capacity.

The Gigalight 1600G CPO adopts an advanced, highly integrated 2.5D hybrid packaging architecture combining Wire Bond (WB) and Flip Chip technologies. This approach significantly reduces package size and overall footprint, improves system performance, lowers power consumption, increases integration density, and enables higher system transmission speeds.

Main Manufacturing Process Flow:

1600G CPO Test Board and CPO Physical Unit

30Jul, 2019

The Evolution Path of Next Generation Data Center’s Optical Interconnection

As a global innovator of optical interconnect design, Gigalight is committed to providing customers with design- and cost-leading high-speed optical interconnect product solutions. Deeply immersed in the field of optical interconnects for more than a decade, Gigalight believes that the upgrade path for next-generation data center optical interconnects should be from 100G to 200G, and then to 400G. Only such smooth upgrades and technological transitions are met the law of market development.

From 100G to 400G, the data center’s network architecture should be firstly upgraded to the most cost-effective 200G SR8/PSM8 architecture (8x 25G NRZ), then to the first generation 400G network architecture—400G PSM8/FR8 (8x 50G PAM4); and at last to the second generation 400G network architecture—400G DR4/FR4 (4x 100G PAM4). Among them, the 200G (8x 25G NRZ) network adopts the mature 25G NRZ electric chip and optical device, which has the same port density as the 100G network, but the bandwidth is doubled, which effectively reduces the transmission cost. In addition, the industrial chain of 25G NRZ optoelectronic chips and optical devices is relatively mature, and the related switches and optical module products are also easier to develop (compared to 50G PAM4), which can help the data center to quickly realize the commercial deployment of 200G networks.

At present, some companies believe that the data center network architecture should be directly upgraded to the second generation 400G, namely the 400G DR4/FR4, so they are rushing to introduce Single Lambda 100G (100G PAM4) or 400G (4x 100G PAM4) optical modules. However, these optical modules require expensive optical components, including Silicon Photonics modulators, EML lasers, and DSP error correction chips. Gigalight believes that it is too early to deploy the 400G DR4/FR4 network architecture in the data center, because the 400G DR4/FR4 products based on Single Lambda 100G PAM4 DSP technology is likely to be out of the Shannon limit, but the 400G PSM8/FR8 products based on 50G PAM4 technology are more likely to meet R&D expectations. The first generation of 400G network (8x 50G PAM4) is easier to commercialize because it adopts 8 channels of 25G linearity optoelectronic chips and related optical devices consistent with the 200G network, except that PAM4 modulation technology is used to achieve doubled bandwidth, and it is just after the 200G NRZ network in the data center network upgrade path.

The network upgrade of the data center should follow the market rules, and there is no such thing as a shortcut to the sky. Gigalight follows the rules of the market, and the 200G (8x 25G NRZ) products that are preferred for data center customers have been validated by North American data center customers. With full R&D design and verification, Gigalight now offers a complete and reliable 200G optical interconnect solution (including the 200G 4x 50G PAM4 series) with the following key benefits in smooth transition to 400G:

Low Power Consumption. With existing 25G NRZ optics, power consumption is as low as 4 watts, while optical modules based on DSP CDR technology can be 2 to 3 watts higher. In this case, saving 2 to 3 watts per 200G optical module is very beneficial for optimizing OPEX and cooling efficiency.
Low Latency. Excellent performance in some special application scenarios such as High Performance Computing (HPC) and High Frequency Trading (HFT).

The 8x 25G NRZ reduces the complexity and design difficulty of the 200G optical module and avoids the development cost and material cost of the difficult DSP. At a broader market level, 100G optical modules have matured and component integration has been established. Similarly, 200G optical modules will also form a cost structure similar to 100G optical modules in the first few years before entering the market, following the downward cost curve. Due to further standardization and automation of component integration and mass production, 200G optical modules are expected to achieve a cost structure comparable to today’s 100G optical modules. Gigalight’s breakthrough in optical packaging technology enables density increases, enabling 200G networks to be quickly and economically deployed commercially!

28Jan, 2019

50G PAM4-based Optical Transceiver Technologies

With the PAM4 encoding technology, the amount of information transmitted on 50G PAM4-based optical transceivers within each sampling cycle doubles. A 25G optical component can be used to achieve a 50Gbps transmission rate, reducing the costs of optical transceivers.

50G PAM4 applies to multiple scenarios, such as single-lane 50GE PAM4 optical transceivers, 4-lane 200GE optical transceivers, and 8-lane 400GE optical transceivers.

Functions

This section introduces the functions of a single-lane 50GE PAM4 optical transceiver.

Working principle of a 50GE PAM4 optical transceiver

The working principle of a 50GE PAM4 optical transceiver is described as follows:

In the transmit direction, the PAM4 encoding chip aggregates two 25Gbit/s NRZ signals into one 25GBaud PAM4 signal. The laser drive chip amplifies the PAM4 signal, and the 25Gbps laser converts the electrical signal into a 25GBaud(50Gbps) single-wavelength optical signal.

In the receive direction, the detector converts the 25GBaud single-wavelength optical signal into an electric signal. The electric signal is shaped and amplified, and then output to the PAM4 decoding chip. The PAM4 decoding chip converts the signal into two 25Gbps NRZ signals.

The 50GE PAM4 optical transceiver uses the QSFP28 encapsulation mode, LC optical interfaces, and single-mode optical fibers. The transmission distance is 10km or 40km, and the maximum power consumption is 4.5W.

Specifications

The performance of transmitters and receivers on optical interfaces of 50GE PAM4 optical transceivers must comply with the IEEE 802.3bs and IEEE 802.3cd standards.

An optical transceiver provides N 25Gbps electrical interfaces. For a 50GE optical transceiver, the two electrical lanes transmit TX1/RX1 and TX2/RX2 signals specified in the SFF-8436_MSA standards. The performance of electrical interfaces must comply with the CEI-28G-VSR LAUI-2 standard.

The optical transceiver with a transmission rate of 50Gbps on a single wavelength supports 50GE, 200GE, and 400GE interfaces. The following table lists the parameters for the 50GE, 200GE, and 400GE technical solutions.

Technical Solutions

Optical Component and Drive Chip

50G PAM4 optical transceivers use mature 25Gbps optoelectronic chips to deliver cost-effective solutions. In 50GBASE-LR 10 km scenarios, uncooled Direct Modulated Laser (DML) Transmitter Optical Sub-Assemblies (TOSAs) with TO packaging are used. Such a solution features mature technologies, low costs, low power consumption, and easy mass production. The linear DML driver chip can convert input PAM4 voltage electric signals into current signals that can directly drive lasers. Such chips deliver a high bandwidth and output large drive current. Their maximum working rate can reach 28GBaud. At the receive end, Receiver Optical Sub-Assemblies (ROSAs) with TO packaging are used. 25Gbps pins and linear Trans-Impedance Amplifier (TIA) chips are integrated to the ROSAs.

Optical components in 50GBASE-LR scenarios

In 50GBASE-ER 40 km scenarios, 25Gbps Electro-absorption Modulated Laser (EML) TOSAs with BOX packaging are used. External cavity modulated Distribution Feed-Back (DFB) lasers, isolators, monitoring diodes, thermistors, and EML components are integrated to the TOSAs and driven by voltage signals. Such a solution features wide linear domains, high ER, high output optical power, and low TDECQ. Linear EML drive chips can amplify input PAM4 signals and output them to next EMLs. These chips provide a high bandwidth, a small jitter, an adjustable output gain, and a working rate up to 28GBaud. At the receive end, APD ROSAs with TO packaging are used. 25Gbps APDs and linear TIA chips are integrated into the ROSAs. Such ROSAs feature high sensitivity and apply to 40km long-distance transmission.

Optical components in 50GBASE-ER scenarios

PAM4 Chip

PAM4 codec chips perform conversion between NRZ signals and PAM4 signals inside transceivers. In the transmit direction, PAM4 chips shape, amplify, and convert two 25Gbps NRZ signals output by boards into one 25GBaud PAM4 signal. In the receive direction, PAM4 chips use the Analog to Digital Converter (ADC) and Digital Signal Processing (DSP) technology to decode the one 25GBaud signal to two 25Gbps NRZ signals.

Differences Between Solutions of NRZ and PAM4 Transceivers

The optical components and chips of PAM4 transceivers are very different from those of NRZ transceivers. The following table lists the differences between 50G QSFP28 LR and 25G SFP28 LR.

The main difference lies in laser drive chips, TIA chips, and data processing chips.

Since PAM4 code has four types of level logic, the laser drive chips and TIA chips are capable of linear outputs. NRZ transceivers output signals in amplitude limiting mode.

PAM4 transceivers use DSP to implement conversion between a 50G PAM4 signal and two 25Gbps NRZ signals. NRZ transceivers transmit data using Clock & Data Recovery (CDR) chips only.